NXP Semiconductors /LPC18xx /SCU /SFSP1_17

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Interpret as SFSP1_17

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FUNCTION_0_DEFAULT)MODE0 (DISABLE_PULL_DOWN)EPD 0 (ENABLE_PULL_UP)EPUN 0RESERVED 0 (DISABLE_INPUT_BUFFER)EZI 0 (ENABLE_INPUT_GLITCH)ZIF 0 (NORMAL_DRIVE_4_MA_D)EHD0RESERVED

EPUN=ENABLE_PULL_UP, EPD=DISABLE_PULL_DOWN, MODE=FUNCTION_0_DEFAULT, EZI=DISABLE_INPUT_BUFFER, ZIF=ENABLE_INPUT_GLITCH, EHD=NORMAL_DRIVE_4_MA_D

Description

Pin configuration register for pins P1_17

Fields

MODE

Select pin function.

0 (FUNCTION_0_DEFAULT): Function 0 (default)

1 (FUNCTION_1): Function 1

2 (FUNCTION_2): Function 2

3 (FUNCTION_3): Function 3

4 (FUNCTION_4): Function 4

5 (FUNCTION_5): Function 5

6 (FUNCTION_6): Function 6

7 (FUNCTION_7): Function 7

EPD

Enable pull-down resistor at pad.

0 (DISABLE_PULL_DOWN): Disable pull-down.

1 (ENABLE_PULL_DOWN): Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode.

EPUN

Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.

0 (ENABLE_PULL_UP): Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.

1 (DISABLE_PULL_UP): Disable pull-up

RESERVED

Reserved

EZI

Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.

0 (DISABLE_INPUT_BUFFER): Disable input buffer

1 (ENABLE_INPUT_BUFFER): Enable input buffer

ZIF

Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.

0 (ENABLE_INPUT_GLITCH): Enable input glitch filter

1 (DISABLE_INPUT_GLITCH): Disable input glitch filter

EHD

Select drive strength.

0 (NORMAL_DRIVE_4_MA_D): Normal-drive: 4 mA drive strength

1 (MEDIUM_DRIVE_8_MA_D): Medium-drive: 8 mA drive strength

2 (HIGH_DRIVE_14_MA_DR): High-drive: 14 mA drive strength

3 (ULTRA_HIGH_DRIVE_20): Ultra high-drive: 20 mA drive strength

RESERVED

Reserved

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